1. Field of the Invention
The present invention relates to a semiconductor device including a field effect transistor and the method of manufacturing thereof, and more particularly, to a semiconductor device including a field effect transistor having a source, a drain, and a channel region in a semiconductor layer formed on an insulation substrate {SOI-MOS (Silicon on Insulator-Metal Oxide Semiconductor)} and a method of manufacturing thereof.
2. Description of the Background Art
A field effect transistor having a source/drain region formed on the surface of a semiconductor substrate such as of silicon is called a bulk MOS. There is another field effect transistor called a SOI-MOS in which the source, drain, and channel regions are formed in a silicon thin film on an insulative thin film or on an insulative substrate such as of sapphire.
FIG. 19 shows a plan view (A) and a sectional view (B) of a conventional SOI-MOS transistor. The sectional view of (B) is taken along line B--B of (A). Referring to FIG. 19, an insulation film 2 is formed on a substrate 1. An island-like silicon semiconductor film 3 is formed on insulation film 2. A channel region 4 including p type impurities of low concentration is formed in semiconductor film 3. A source region 12 and a drain region 8 including n type impurities of high concentration are formed adjacent to one side and the other side of channel region 4. A gate insulation film 5 is formed on channel region 4. A gate electrode 6 is formed on gate insulation film 5. Semiconductor film 3 and gate electrode 6 are coated with an interlayer insulation film 9. Interlayer insulation film 9 has a contact hole 10 formed therein. A conductive layer 11 is provided to contact source region 12 and drain region 8 via each contact hole 10.
The operation of a conventional SOI-MOS transistor of the above-described structure will be explained hereinafter.
On applying positive voltage to gate electrode 6, electrons are attracted as n type carriers in the proximity of gate electrode insulation film 5 at the upper portion of channel region 4. The region having electrons attracted is inverted to the n type which is identical to those of source region 12 and drain region 8. As a result, current can flow between source region 12 and drain region 8. The electrons drawn by the gate voltage moves from source region 12 to drain region 8 due to the difference of voltage applied to source region 12 and drain region 8. That is to say, current flows from drain region 8 to source region 12. The density of the attracted electrons vary with the voltage applied to gate electrode 6. Therefore, the current flowing across channel region 4 can be controlled by the gate voltage.
The following problems are encountered in the operation of such a SOI-MOS transistor. FIG. 20 schematically shows a sectional view of a conventional SOI-MOS transistor for describing the mechanism of destruction of the transistor. Referring to FIG. 20, potential difference is applied between the source and drain, and positive voltage is applied to the gate to bring the SOI-MOS transistor into operation. If the drain voltage is increased at this time, the electric field in the direction of the channel increases significantly in the proximity of the drain. The electrons injected into the channel region from the source region (a of FIG. 20) are accelerated by this high electric field to easily become more energetic. These highly energetic electrons collide with the lattice of the silicon in the proximity of the end of the drain region, as shown in FIG. 20, to generate in an avalanche manner a quantity of electron-hole pairs. Electrons and holes are generated by this collision ionization (impact ionization; b of FIG. 20), whereby these electrons are drawn towards the high drain electric field into the drain region to become a portion of the drain current. The generated holes are pushed back by the drain electric field to flow and accumulate in the depletion layer beneath the channel region or in the lower portion of the channel region in the proximity of the source region (c of FIG. 20). Such a phenomenon is seen not only in a MOS transistor of a short channel length, but also in that having a relatively long channel length. Particularly in a MOS transistor of a short channel length, a great amount of electron-hole pairs are generated in comparison with that of a MOS transistor having a long channel length.
Thus, the potential of the channel region rises when the holes generated by impact ionization flow into and accumulate in the lower portion of the channel region. The threshold voltage of the MOS transistor is decreased. This induces a kink effect as shown in FIG. 21 of the drain current versus voltage characteristic. A kink effect is a phenomenon where the drain current does not saturate substantially to a constant value, but shows a sudden increase as the drain voltage is increased. In the case of an n channel type MOS transistor, for example, the increase of the drain voltage will cause the holes of the electron-hole pairs generated by impact ionization and the like of the channel carriers to accumulate in the channel region, whereby the channel region is biased positively to decrease the threshold voltage. As a result, the drain current suddenly increases. In plotting this drain current with respect to the drain voltage, a kink is seen in the high current region, to be termed a kink effect. This kink effect is described in detail in, for example, JENO TIHANYI and HEINRICH SCHLOTTERER "Properties of ESFI MOS Transistors Due to the Floating Substrate and the Finite Volume" IEEE TRANSACTIONS on ELECTRON DEVICES, VOL. ED-22, No. 11, pp. 1017-1023 NOVEMBER 1975. In particular, this kink effect is different in degrees between devices.
When holes generated by impact ionization are accumulated in the lower portion of the channel region, the potential of the channel region and in the proximity of the source region is further increased by the accumulated holes. This decreases the potential difference between the channel region and the source region. The decrease of the potential barrier in the proximity of the source region will cause many electrons to be injected from the source region to the channel region. This causes furthermore electron-hole pairs to be generated since the impact ionization becomes more significant. The generated holes will further decrease the potential barrier in the proximity of the source region to further increase electrons injected from the source region, so that finally breakdown occurs in the MOS transistor.
Because the MOS transistor is formed on an insulative substrate or film according to the SOI-MOS structure, the substrate region (channel region) of the MOS transistor is electrically at a floating state. When the drain voltage is increased, the holes of the electron-hole pairs generated by impact ionization of the channel carriers in the case of, for example, an n channel type MOS transistor, accumulates in the substrate region to bias positively the substrate region. Therefore, the threshold voltage is decreased to result in a sudden increase in the drain current. Thus, the potential of the substrate region of such a SOI-MOS transistor is unstabilized. This phenomenon is called the substrate floating effect.
The above phenomenon can be described using a band diagram of the energy band of a semiconductor where holes generated by impact ionization is accumulated in the lower portion of the channel region. The band diagram will be schematically described with reference to FIG. 22. The electrons in solids cannot take all energy levels. There is an allowed band of an energy range where electrons in solids can exist. There is also a forbidden band of energy range where electrons in solids cannot exist. The structure of the allowed band and the forbidden band differ according to the types and configuration of atoms forming the object substance. For example, monocrystals of silicon and germanium have a tetrahedral atomic configuration. Such a monocrystal of a semiconductor has an empty tolerance band (conduction band) where no electrons exist at absolute zero via a forbidden band above an allowed band (valence band) completely filled by electrons. This structure is shown in FIG. 22(A). The conduction band exists above the valence band by a forbidden energy band gap width (band gap) E.sub.g of an energy level. In absolute zero (T=0K), the electrons of the above-described semiconductor usually do not contribute to electrical conduction and behave as insulators.
However, since forbidden energy band gap width E.sub.g is a finite value (several eV), electrons of the completely filled valence band are excited to the conduction band above the forbidden band by thermal function if not at absolute zero. This situation is shown in FIG. 22(B). The excited electrons can move relatively freely in the conduction band above the forbidden band. Therefore, these excited electrons can contribute to electrical conduction. In the valence band beneath the forbidden band, the shortage of electrons will cause the travel of holes.
The electrical conduction of a semiconductor is caused by the travel of excited electrons to the conduction band which is the allowed band above the forbidden band, and the travel of holes in the valence band which is the allowed band beneath the forbidden band. The value of forbidden energy band gap width E.sub.g depends upon the substance, which is for example, 1.1 eV for silicon (Si), 0.66 eV for germanium (Ge), 1.27 eV for indium phosphorus (InP), 2.25 eV for gallium phosphorus (GAP), and 1.43 eV for gallium arsenide (GaAs).
By adding impurities into a semiconductor for forming an energy level in the forbidden band, the electron density of the conduction band above the forbidden band and the hole density of the valence band beneath the forbidden band can be controlled.
For example, by adding boron into the silicon, the boron forms an energy level higher by 0.045 eV on the valence band entirely filled with silicon electrons. Because boron is trivalent with one valence electron fewer than that of the tetravalent silicon, the electrons are easily excited from the valence band beneath the forbidden band to the energy level of boron by 0.045 eV due to thermal effect. This generates the state of many electron shortage i.e. holes in the valence band of the forbidden band. This is shown in FIG. 22(C). The density of the holes can be controlled by the amount of impurities added.
Another example is considered where arsenic is added into the germanium. Arsenic will form below the conduction band of the germanium an energy level lower by 0.013 eV. Because arsenic is pentavalent with one more valence electron than that of the tetravalent germanium, electrons are easily excited from the energy level of the arsenic to the conduction band above the forbidden band by 0.013 eV by thermal effect. Thus, many electrons are generated in the conduction band above the forbidden band. This situation is shown in FIG. 22(D). The density of electrons can be controlled by the amount of impurities added.
The impurities added to the semiconductor serve only to receive electrons from the valence band beneath the forbidden band of the semiconductor or to provide electrons to the conduction band above the forbidden band.
The silicon having boron added, for example, as described above, is called a p type semiconductor. The germanium having arsenic added is called an n type semiconductor. The energy band of a p type semiconductor is shown in FIG. 22(E), and the energy band of an n type semiconductor is shown in FIG. 22(F). An energy level having an existence probability of 1/2 of electrons within a semiconductor is defined Fermi level E.sub.F. The Fermi level is located substantially in the middle of the forbidden band in a semiconductor that does not include impurities. In the case where p type impurities such as boron are added, the Fermi level E.sub.F moves to the side of the valence band beneath the forbidden band since there is an overall shortage of electrons, as shown in (E) of FIG. 22. In the case where n type impurities such as arsenic are added, the Fermi level E.sub.F moves to the side of the conduction band above the forbidden band due to the entire increase of electrons, as shown in (F) of FIG. 22.
The formation of a pn junction with a p type semiconductor and an n type semiconductor having the above described energy bands results in the energy band of FIG. 23. FIG. 23 shows a band diagram of a pn junction where an n.sup.+ region and a p.sup.- region are respectively formed in the silicon. The Fermi level E.sub.F must be identical in the entire pn junction due to the thermal equilibrium state. It can be seen from FIG. 23 that the energy level E.sub.C of the lowest end of the conduction band and the energy level E.sub.V of the highest end of the valence band respectively show a curve configuration in the boundary regions x.sub.n and x.sub.p of the pn junction.
Consider the pn junction of FIG. 23 having the n.sup.+ region correspond to source region 12, and the p.sup.- region correspond to channel region 4 of FIG. 19. Holes existing in the lower portion of the channel region cannot flow into the source region since there is a potential barrier V.sub.b between the channel region and the source region. It is therefore considered that holes generated by impact ionization are accumulated in the lower portion of the channel region.
Since a conventional SOI-MOS transistor is configured as described above, holes generated by impact ionization are accumulated in the lower portion of the channel region. This induces the problem that the potential in the channel region is increased to decrease the breakdown voltage between the source and drain of a MOS transistor.
The decrease of breakdown voltage between the source and drain is caused by the substrate floating effect particular to a SOI-MOS structure. Since the potential barrier V.sub.b between the source region and the channel region is great, as shown in the band diagram of FIG. 23, there is an inherent problem that the holes accumulated in the lower portion of the channel region could not be removed.